The present invention relates to a semiconductor memory device provided with an address transition detection (ATD) circuit for detecting a transition in an externally provided address signal, and more particularly, to a semiconductor memory device and control method composed so as to perform a refresh operation and read/write operation using a pulse signal output from an ATD circuit as a trigger.
In the past, so-called pseudo SRAM were used as semiconductor memory devices composed so as to be able to be handled in the manner of SRAM (Static Random Access Memory) despite consisting primarily of DRAM (Dynamic Random Access Memory). These pseudo SRAM employ an internal synchronization scheme that operates by detecting a transition in an address signal, and are equipped with an address transition detection circuit (abbreviated as ATD circuit, or address transition detector) for detecting a transition in an externally provided address signal. In the case of this pseudo SRAM, although it is difficult to obtain high-speed performance in the manner of regular SRAM having memory cells comprised of flip-flops since it consists primarily of DRAM, pseudo SRAM are able to realize large-scale storage capacity comparable to DRAM.
FIG. 7 shows an example of the configuration of an address input system of a pseudo SRAM provided with an ATD circuit. Address signals ADD0 to ADDn (n is a natural number) are address signals applied from the outside. Address input circuits 800-0 to 800-n are provided corresponding to these address signals ADD0 through ADDn, and each of these address input circuits is composed of an input buffer 801 and latch circuit 802. In addition, ATD circuits 810-0 to 810-n are provided for the outputs of each address input circuit, and each of the output signals of these ATD circuits are input to pulse generator 820.
Here, input buffers 801 of address input circuits 800-0 to 800-n receive externally provided address signals (ADD0 to ADDn), and convert them to internal device address signals. In addition, latch circuits 802 latch address signals output from input buffers 801 based on a control signal output from a prescribed control circuit system not shown in the case an external address signal has changed, and normally, allow the output signals of input buffers 801 to pass through as internal address signals (IA0 to IAn).
ATD circuits 810-0 to 810-n generate positive one-shot pulses xcfx860 to xcfx86n by detecting a change (transition) in internal address signals IA0 to IAn output from latch circuits 802 of address input circuits 800-0 to 800-n. Pulse generator 802 receives one-shot pulses xcfx860 to xcfx86n output from ATD circuits 810-0 to 810-n, and generates a pulse address transition detection signal xcfx86a having a prescribed pulse width. Various types of control signals required for operation of each section are then derivatively generated based on this pulse address transition detection signal xcfx86a.
According to a semiconductor memory device of the background art equipped with this type of address input system, in the case address signals ADD0 to ADDn provided from the outside are in a steady state without changing, address signals incorporated from the outside through input buffers 801 in each of address input circuits 800-0 to 800-n pass through latch circuits 802 in the through state, and are provided to, for example, a pre-decoding circuit of a latter stage as internal address signals IA0 to IAn. In this state, since there is no change in the address signals, ATD circuits 810-0 to 810-n do not generate one-shot pulses xcfx860 to xcfx86n, and pulse address transition detection signal xcfx86a is held at the low (L) level.
In FIG. 7, if, for example, an externally provided address signal ADD0 changes from this state, internal address signal IA0 output from input buffer 801 through latch circuit 802 in the through state changes. ATD circuit 810-0 detects this change in address signal IA0, and generates one-shot pulse xcfx860. Pulse generator 802 then receives one-shot pulse xcfx860 generated with ATD circuit 810-0, and outputs a pulse signal as pulse address transition detection signal xcfx86a.
Similarly, if other externally provided address signals ADD1 to ADDn change, pulse generator 802 receives a one-shut pulse generated with each ATD circuit, and outputs pulse address transition detection signal xcfx86a. Control signals required for memory cell refresh operation or control signals required for read/write operation are generated in a control signal generation circuit system not shown in the drawings based on this pulse address transition detection signal xcfx86a, and various operations within the device are controlled at the appropriate timing.
However, in the case of the above pseudo SRAM, due to its specifications, a constitution is employed in which both the operations of refresh operation and read/write operation are performed consecutively within the same cycle based on a common pulse address transition detection signal xcfx86a. Consequently, if noise is contained in externally provided address signals ADD0 to ADDn, one-shut pulses xcfx860 to xcfx86n are generated following a malfunction of ATD circuits 810-0 to 810-n due to this noise. As a result, the refresh operation and read/write operation are consecutively performed incorrectly, and since the majority of the circuits that compose the semiconductor memory device operate, a large operating current is generated that results in the problem of increased current consumption.
A first example of the background art that attempts to solve problems caused by this type of ATD circuit malfunction is the semiconductor memory device disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 3-12095. This semiconductor memory device is provided with a first address transition detection circuit that generates a pulse signal for controlling the read operation until immediately before an output buffer, and a second address transition detection circuit that generates a pulse signal for controlling operation beyond the output buffer, and a filter is provided in a prior stage of this second address transition detection circuit for removing noise contained in address signals.
According to this device, even if apparent noise is contained in address signals caused by fluctuation in ground potential Vss accompanying operation of the output buffer, this noise is removed by a filter. Thus, the second address transition detection circuit that generates a pulse signal for controlling output buffer operation does not malfunction due to this noise, and malfunction of the output buffer also no longer occurs caused by spontaneously generated ground potential noise. In addition, in this device, since the operation of the circuit system until immediately before the output buffer, which determines the majority of read time, is controlled by a pulse signal from the first address transition detection circuit that inputs address signals without going through a filter, high-speed performance is not impaired. However, this semiconductor memory device according to this first example of the background art prevents malfunctions caused by fluctuation of ground potential Vss accompanying output buffer switching, and in the case the refresh operation and read/write operation are performed within the same cycle, is unable to suppress the generation of operating current caused by noise contained in an address.
In addition, a second example of a device according to the background art is the semiconductor integrated circuit disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 5-81888. This semiconductor integrated circuit is provided with an ATD circuit (to be referred to as the first ATD circuit) for detecting transitions in address signals, a noise filter for removing noise from addresses, and an ATD circuit (to be referred to as the second ATD circuit) for detecting transitions in address signals from which noise has been removed by the noise filter. The former first ATD circuit is used for control of internal operation at the stage before the output buffer (latching of data), while the latter second ATD circuit is used for control of the output signal in the state prior to a regular output signal being output (output preset).
According to this second example of the background art, in the reading of data, the output level of the output buffer slowly changes from high (H) to low (L) under the control of the pulse signal output from the second ATD circuit. As a result, ground noise during reading of xe2x80x9cLxe2x80x9d is reduced. In addition, tolerance to power source noise is improved by latching data until that time internally under the control of a pulse signal output from the first ATD circuit. In addition, erroneous preset of output caused by power source noise is prevented by removing power source noise with a noise filter. However, this second example of the background art also prevents malfunctions caused by noise accompanying output buffer switching, and similar to the first example of the background art mentioned above, in the case the refresh operation and read/write operation are performed within the same cycle, the generation of operating current caused by noise contained in address signals cannot be suppressed.
In consideration of the above circumstances, the object of the present invention is to provide a semiconductor memory device and control method that is capable of effectively suppressing the generation of operating current caused by noise of address signals provided from the outside without inhibiting operating speed during reading and writing.
In order to solve the above problems, the semiconductor memory device according to the present invention is provided with: a memory cell array composed by arranging memory cells containing data storage capacitors in a matrix; a filter circuit that removes noise contained in an address signal provided from the outside (for example, a constituent feature corresponding to noise filter circuit 102 to be described later); a first signal transition detection circuit system that generates a first pulse signal for controlling refresh operation by detecting a change in an address signal prior to passing through the filter circuit (for example, a constituent feature corresponding to the circuit system composed of address transition detection circuit 311 and pulse composition circuit 312 to be described later); a second signal transition detection circuit system that generates a second pulse signal for controlling read/write operation by detecting a change in an address signal after passing through the filter circuit (for example, a constituent feature corresponding to a circuit system composed of an address transition detection circuit 321 and a pulse composition circuit 322 to be described later); and a control system that sequentially performs the refresh operation and the read/write operation within the same cycle by using the first and second pulse signals as triggers.
According to this constitution, the refresh operation is started in the case a change is detected in an address signal prior to passing through the filter circuit, and a normal read/write operation is started in the case a change is detected in an address signal after having passed through the filter circuit. Here, in the case noise is contained in an address signal provided from the outside, that address signal is provided to the second signal transition detection circuit system following removal of that noise by the filter circuit. Thus, the second address signal is not output due to noise contained in the address signal, and there is no malfunction of starting the read/write operation. In addition, since noise is contained in address signals prior to passing through the filter circuit, the first signal transition detection circuit system that inputs this address signal outputs a first pulse signal, and the refresh operation is started. Namely, in the case noise is contained in an address signal provided from the outside, only the refresh operation is performed, while the read/write operation is not performed.
In contrast, in the case noise is not contained in an address signal provided from the outside, a change in the external address signal is respectively detected by the first and second signal transition detection circuit systems, and first and second pulse signals are output. The refresh operation and read/write operation are then sequentially performed within the same cycle by using these first and second pulse signals as triggers. At this time, the second pulse signal is output at a delay relative to the first pulse signal that is equal to the delay time in the filter circuit. However, since the read/write operation is performed in succession after the refresh operation, there is no problem with the second pulse signal that serves as the trigger of the read/write operation being delayed relative to the first pulse signal that serves as the trigger of the refresh operation, and the operating speed of the read/write operation is not impaired.
Thus, according to this constitution, even if noise is contained in an address signal, and an apparent change has occurred in the address signal due to this noise, the generation of operating current due to the read/write operation can be suppressed, and there is also no impairment of operating speed of the normal read/write operation.
In the semiconductor memory device according to the present invention, the second signal transition detection circuit system may be made to, for example, control the first signal transition detection circuit system in an inactive state by detecting a change in an address signal that has passed through the filter circuit. According to this constitution, even if noise is generated in an address signal during read/write operation following refresh operation, a first pulse signal is not output from the first signal transition detection circuit system. Thus, the refresh operation is not erroneously started during the read/write operation, and destruction of data can be prevented.
Moreover, in the semiconductor memory device according to the present invention, the control system may be made to, for example, control the refresh operation based on the first pulse signal, while also controlling the read/write operation based on the second pulse signal (for example, a constituent feature corresponding to the circuit system containing an address multiplexer 5 to be described later). According to this constitution, the refresh operation is able to start by using a first pulse signal as a trigger, while the read/write operation is able to start by using a second pulse signal as a trigger.
Moreover, in the semiconductor memory device according to the present invention, a row decoder circuit for selecting a row of the memory cell array is additionally provided, and the control system may be composed to include an address multiplexer (for example, a constituent feature corresponding to address multiplexer 5 to be described later) that selects either a read/write address signal generated from an address signal that has passed through the filter circuit or a refresh address signal generated in advance within the device based on the first and second pulse signals, and supplies a selected address signal to the row decoder circuit. According to this constitution, in the case a change is detected in an address signal provided from the outside, a refresh address signal can be supplied to the row decoder based on the first pulse signal, and a read/write address signal can be supplied to the row decoder based on the second pulse signal. Thus, the required address signals can be obtained in each of the refresh and read/write operations.
Moreover, in the semiconductor memory device according to the present invention, the filter circuit may be composed to, for example, include a delay circuit having a delay amount corresponding to the pulse width of presumed noise targeted for removal. According to this constitution, the delay time in the filter can be held to the required minimum amount for removal of noise contained in the address signal. Thus, the apparent decrease in sensitivity of the second signal transition detection circuit system that includes the filter circuit can be held to a minimum.
Moreover, in the semiconductor memory device according to the present invention, the filter circuit may be a flip-flop that directly inputs the address signal from the outside. According to this constitution, noise does not substantially penetrate inside as long as the stable state of the flip-flop is not inverted. Thus, the operation of the second signal transition detection circuit system that detects changes in a signal that has passed through the filter circuit can be further stabilized.
Moreover, in the semiconductor memory device according to the present invention, the filter circuit may, for example, have characteristics that remove noise that causes an address signal provided from the outside to change to the H level in the case the address signal is at the L level. According to this constitution, in the case, for example, the ground level inside the semiconductor memory device has fluctuated, apparent noise generated in the address signal can be removed.
Moreover, in the semiconductor memory device according to the present invention, the second signal transition detection circuit system may be made to prohibit read/write operation by the control system by detecting a change in an address signal that has passed through the filter circuit.